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description the a1250 hall-effect sensor ic is a temperature stable, stress-resistant bipolar switch. this device is the most sensitive hall-effect device in the allegro? bipolar switch family and is intended for ring-magnet sensing. superior high-temperature performance is made possible through an allegro patented dynamic offset cancellation that utilizes chopper-stabilization. this method reduces the offset voltage normally caused by device overmolding, temperature dependencies, and thermal stress. the a1250 includes the following on a single silicon chip: a voltage regulator, hall-voltage generator, small-signal amplifier, chopper stabilization, schmitt trigger, and a short circuit protected open-drain output. advanced bicmos wafer fabrication processing takes advantage of low-voltage requirements, component matching, very low input-offset errors, and small component geometries. the a1250 hall-effect bipolar switch turns on in a south polarity magnetic field of sufficient strength and switches off in a north polarity magnetic field of sufficient strength. because the output state is not defined if the magnetic field is diminished or removed, to ensure that the device switches, allegro recommends using magnets of both polarities and of sufficient strength in the application. a1250-ds, rev. 1 features and benefits ? high speed, 4-phase chopper stabilization ? low operating voltage down to 3.0 v ? high sensitivity ? stable switchpoints ? robust emc hall effect latch / bipolar switch functional block diagram a1250 control current limit clock / logic low-pass filter 1 regulator gnd vc v+ c vout dynamic offset cancellation sample and hold to all subcircuits amp not to scale packages: 3-pin sot23w (suffix lh), and 3-pin sip (suffix ua) continued on the next page?
hall effect latch / bipolar switch a1250 2 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pin-out diagrams absolute maximum ratings characteristic symbol notes rating unit* forward supply voltage v cc 28 v reverse supply voltage v rcc ?18 v output off voltage v out 28 v reverse output voltage v rout ?0.6 v output current i outsink internally limited a reverse output current i rout ?10 ma magnetic flux density b unlimited g operating ambient temperature t a range l ?40 to 150 oc maximum junction temperature t j (max) 165 oc storage temperature t stg ?65 to 170 oc *1 g (gauss) = 0.1 mt (millitesla). terminal list table name number function package lh package ua vcc 1 1 device supply vout 2 3 device output gnd 3 2 ground the a1250 is rated for operation in the ambient temperature range l, ?40c to 150c. two package styles provide magnetically optimized solutions for most applications. each package is lead (pb) free version, with 100% matte tin plated leadframe. description (continued) selection guide part number packing * mounting ambient, t a (c) a1250llhlt-t 7-in. reel, 3000 pieces/reel surface mount ?40 to 150 A1250LLHLX-T 13-in. reel, 10 000 pieces/reel surface mount a1250lua-t bulk, 500 pieces/bag sip through hole * contact allegro for additional packing options. 1 2 3 gnd vout vcc 1 3 2 gnd vout vcc package ua package lh
hall effect latch / bipolar switch a1250 3 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics supply voltage v cc operating t j < 165c 3.0 ? 24 v output leakage current i outoff v out = 24 v, b < b rp ??10 a output on voltage v out(sat) i out = 20 ma, b > b op ? ? 500 mv output current limit i om b > b op 30?60ma power-on time t po v cc > 3.0 v ? ? 25 s chopping frequency f c ? 160 ? khz output rise time 1 t r r load = 820 , c s = 20 pf ? ? 2 s output fall time 1 t f r load = 820 , c s = 20 pf ? ? 2 s supply current i ccon b > b op ??4ma i ccoff b < b rp ??4ma reverse battery current i rcc v rcc = ?18 v ? ? ?2 ma supply zener clamp voltage v z i cc = 6.5 ma, t a = 25c 28 ? ? v supply zener current i z v cc = 28 v ? ? 7 ma magnetic characteristics 2 valid at t a = ?40c to 150c, t j t j (max), unless otherwise noted operate point b op ?10 5 25 g release point b rp ?25 ?5 10 g hysteresis b hys 51025 g 1 guaranteed by design. 2 magnetic flux density, b, is indicated as negative value for north-polarity fields, and positive for south-polarity fields. operating characteristics valid at t a = ?40c to 150c, c bypass = 0.1 f, unless otherwise noted characteristics symbol test conditions min. typ. max. unit
hall effect latch / bipolar switch a1250 4 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value units package thermal resistance r ja package lh, 1-layer pcb with copper limited to solder pads 228 oc/w package lh, 2-layer pcb with 0.463 in. 2 of copper area each side connected by thermal vias 110 oc/w package ua, 1-layer pcb with copper limited to solder pads 165 oc/w *additional thermal information available on allegro web site. 6 7 8 9 2 3 4 5 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 20 40 60 80 100 120 140 160 180 temperature (oc) maximum allowable v cc (v) p ower d era ti ng c urve (r q ja = 228 oc/w) 1-layer pcb, package lh (r q ja = 110 oc/w) 2-layer pcb, package lh (r q ja = 165 oc/w) 1-layer pcb, package ua v cc(min) v cc(max) 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 20 40 60 80 100 120 140 160 180 temperature (c) power dissipation, p d (m w) power dissipation versus ambient temperature (r q ja = 165 oc/w) 1-layer pcb, package ua (r q ja = 228 oc/w) 1-layer pcb, package lh (r q ja = 110 oc/w) 2-layer pcb, package lh
hall effect latch / bipolar switch a1250 5 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristic performance data 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 5 10 15 20 25 i ccon (ma) v cc (v) supply current (on) versus supply voltage -40c 25c 150c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -50 -25 0 25 50 75 100 125 150 i ccon (ma) t a (c) supply current (on) versus ambient temperature v cc : 24 v v cc : 3 v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 5 10 15 20 25 i ccoff (ma) v cc (v) supply current (off) versus supply voltage -40c 25c 150c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -50 -25 0 25 50 75 100 125 150 i ccoff (ma) t a (c) supply current (off) versus ambient temperature v cc : 24 v v cc : 3 v 0 50 100 150 200 250 300 350 400 450 500 -50 -25 0 25 50 75 100 125 150 v out(sat) t a (c) v out(sat) versus ambient temperature i out = 20 ma v cc : 3 v v cc : 24 v
hall effect latch / bipolar switch a1250 6 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com -10 -5 0 5 10 15 20 25 -50 -25 0 25 50 75 100 125 150 b op (g) t a (c) operate point versus ambient temperature v cc : 24 v v cc : 3 v -25 -20 -15 -10 -5 0 5 10 -50 -25 0 25 50 75 100 125 150 b rp (g) t a (c) release point versus ambient temperature v cc : 24 v v cc : 3 v 5 7 9 11 13 15 17 19 21 23 25 -50 -25 0 25 50 75 100 125 150 b op (g) t a (c) hysteresis versus ambient temperature v cc : 24 v v cc : 3 v
hall effect latch / bipolar switch a1250 7 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description the output of this device switches low (turns on) when a magnetic field perpendicular to the hall sensor ic exceeds the operate point threshold, b op . after turn-on, the output voltage is v out(sat) . the output transistor is capable of sinking current up to the short circuit current limit i om , which is a minimum of 30 ma. when the magnetic field is reduced below the release point, b rp , the device output goes high (turns off). the difference in the magnetic operate and release points is the hysteresis, b hys , of the device. this built-in hysteresis allows clean switching of the output even in the presence of external mechanical vibration and electrical noise. given the magnetic parameter specifications (refer to magnetic characteristics table), bipolar switches will operate in one of three modes, depending on switchpoints. for typical values of b op and b rp , the device will operate as a latch, as shown in figure 1a. note that, when the magnetic flux density exceeds a switchpoint, the output will retain its state when the magnetic field is removed. the other two modes of operation are the unipolar switch and the negative switch, shown in panels 1b and 1c, respectively. the unipolar switch type operates only in a south polarity field, and will switch to the high state if the magnetic field is removed. the negative switch operates only in a north polarity field, and will switch to the low state if the magnetic field is removed. individual bipolar switch devices exhibit any one of the three switching behaviors: latch, unipolar, or negative switch. because these devices are not guaranteed to behave as latches, magnetic fields of sufficient magnitude and alternate polarity are required to ensure output switching. powering up the device in the hysteresis band, that is in a mag- netic field less than b op and higher than b rp , allows an indeter- minate output state. note that this hysteresis band encompasses zero magnetic field on devices that exhibit latch behaviors. the correct state is determined after the first magnetic excursion beyond b op or b rp . figure 1. bipolar device output switching modes. these behaviors can be exhibited when using a circuit such as that shown in figure 1. panel a displays the hysteresis when a device exhibits latch mode (note that the b hys band incorporates b = 0), panel b shows unipolar switch behavior (the b hys band is more positive than b = 0), and panel c shows negative switch behavior (the b hys band is more negative than b = 0). bipolar devices, such as the a1250, can operate in any of the three modes. b op b rp b hys v out v out(sat) switch to low switch to high v+ 0 b op b rp b hys v out v out(sat) switch to low switch to high v+ 0 b op b rp b hys v out v out(sat) switch to low switch to high v+ 0 v cc v cc v cc b+ b? b+ b? 0 0 b+ b? 0 (a) (b) (c)
hall effect latch / bipolar switch a1250 8 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com application information figure 2. typical application circuit figure 3. concept of chopper stabilization technique chopper stabilization technique when using hall-effect technology, a limiting factor for switchpoint accuracy is the small signal voltage developed across the hall element. this voltage is disproportionally small relative to the offset that can be produced at the output of the hall sensor ic. this makes it difficult to process the signal while maintain- ing an accurate, reliable output over the specified operating temperature and voltage ranges. chopper stabilization is a unique approach used to minimize hall offset on the chip. allegro employs a patented technique to remove key sources of the out- put drift induced by thermal and mechanical stresses. this offset reduction technique is based on a signal modulation-demodula- tion process. the undesired offset signal is separated from the magnetic field-induced signal in the frequency domain, through modulation. the subsequent demodulation acts as a modulation process for the offset, causing the magnetic field-induced signal to recover its original spectrum at base band, while the dc offset becomes a high-frequency signal. the magnetic-sourced signal then can pass through a low-pass filter, while the modulated dc offset is suppressed. in addition to the removal of the thermal and stress related offset, this novel technique also reduces the amount of thermal noise in the hall sensor ic while completely removing the modulated residue resulting from the chopper operation. the chopper stabilization technique uses a high frequency sampling clock. for demodulation process, a sample and hold technique is used. this high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. this approach desensitizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent hall output voltages and precise recoverability after temperature cycling. this technique is made possible through the use of a bicmos process, which allows the use of low-offset, low-noise amplifiers in combination with high- density logic integration and sample-and-hold circuits. amp regulator clock/logic hall element tuned filter anit-aliasing lp filter vcc v+ ic output gnd vout c bypass 0.1 f r load a1250
hall effect latch / bipolar switch a1250 9 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the device must be operated below the maximum junction temperature of the device, t j (max) . under certain combina- tions of peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the application. this section presents a procedure for correlating factors affecting operating t j . (thermal data is also available on the allegro microsystems web site.) the package thermal resistance, r ? ja , is a figure of merit sum- marizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. its primary component is the effective thermal conductivity, k, of the printed circuit board, including adjacent devices and traces. radiation from the die through the device case, r ? jc , is relatively small component of r ? ja . ambient air temperature, t a , and air motion are significant external factors, damped by overmolding. the effect of varying power levels (power dissipation, p d ), can be estimated. the following formulas represent the fundamental relationships used to estimate t j , at p d . p d = v in i in (1) ?? ? t = p d r ? ja (2) t j = t a + t (3) for example, given common conditions such as: t a = 25c, v in = 12 v, i in = 4 ma, and r ? ja = 140 c/w, then: p d = v in i in = 12 v 4 ma = 48 mw ?? t = p d r ? ja = 48 mw 140 c/w = 7c t j = t a + ? t = 25c + 7c = 32c a worst-case estimate, p d (max) , represents the maximum allow- able power level, without exceeding t j (max) , at a selected r ? ja and t a . example : reliability for v cc at t a = 150c, package ua, using a single-layer pcb. observe the worst-case ratings for the device, specifically: r ? ja = 165 c/w, t j (max) = 165c, v cc (max) = 24 v, and i cc (max) = 4 ma. calculate the maximum allowable power level, p d (max) . first, invert equation 3: ? t max = t j (max) ? t a = 165 c ? 150 c = 15 c this provides the allowable increase to t j resulting from internal power dissipation. then, invert equation 2: ???? p d (max) = ? t max r ? ja = 15c 165 c/w = 91 mw finally, invert equation 1 with respect to voltage: v cc (est) = p d (max) i cc (max) = 91 mw 4 ma = 23 v the result indicates that, at t a , the application and device can dissipate adequate amounts of heat at voltages v cc (est) . compare v cc (est) to v cc (max) . if v cc (est) v cc (max) , then reliable operation between v cc (est) and v cc (max) requires enhanced r ? ja . if v cc (est) v cc (max) , then operation between v cc (est) and v cc (max) is reliable under these condi- tions. power derating
hall effect latch / bipolar switch a1250 10 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lh 3-pin sot23w 0.55 ref gauge plane seating plane 0.25 bsc 0.95 bsc 0.95 1.00 0.70 2.40 2 1 a active area depth, 0.28 mm ref b c c b reference land pattern layout all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances branding scale and appearance at supplier discretion a pcb layout reference view standard branding reference view 1 branded face n = last three digits of device part number nnn 2.90 +0.10 ?0.20 44 8x 10 ref 0.180 +0.020 ?0.053 0.05 +0.10 ?0.05 0.25 min 1.91 +0.19 ?0.06 2.98 +0.12 ?0.08 1.00 0.13 0.40 0.10 for reference only; not for tooling use (reference dwg-2840) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown d hall element, not to scale d d d 1.49 0.96 3
hall effect latch / bipolar switch a1250 11 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package ua 3-pin sip 23 1 1.27 nom 2.16 max 0.51 ref 45 c 45 0.79 ref b e e e 2.04 1.44 gate burr area a b c dambar removal protrusion (6x) a d e d branding scale and appearance at supplier discretion hall element, not to scale active area depth, 0.50 mm ref for reference only; not for tooling use (reference dwg-9049) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown standard branding reference view = supplier emblem n = last three digits of device part number nnn 1 mold ejector pin indent branded face 4.09 +0.08 ?0.05 0.41 +0.03 ?0.06 3.02 +0.08 ?0.05 0.43 +0.05 ?0.07 15.75 0.51 1.52 0.5
hall effect latch / bipolar switch a1250 12 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?2010-2013, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions a s may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, llc assumes n o re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com revision history revision revision date description of revision rev. 1 march 22, 2012 update product selection

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